In systems using memory devices, such as ROMs, DRAMs, SRAMs, or the like, a memory controller is used for controlling access to the memory devices according to requests from other devices, such as a processor or a direct memory access (DMA) controller. Typically, memory devices do not generate outputs used for handshaking operations in sending or receiving data. In systems using these types of memory devices, the handshaking operations in data transfers involving the memory devices are performed by the memory controller. Memory controllers frequently include internal hardware, such as counters or timers, that perform a timing function to ensure that control signals, address information, or data is delivered to or taken from the appropriate bus at the correct time. When different types of memory devices are used in the system, this can lead to complexity because of the different timing requirements of different memory devices. In addition, using memory devices having different timing requirements can result in reduced utilization of the bus. A need exists for a device and a method for using the device that will improve the utilization of the bus.